1. Field of the Invention
The present invention relates to a digital time-division switching system. More particularly, it relates to the improvement of each memory portion of time switches and a space switch of a three-stage (Time-Space-Time) time-division switching system.
2. Description of the Prior Art
A digital time-division switching system broadly uses Time-Space-Time switches, i.e., primary time switches, a space switch, and secondary time switches. Each of the primary time switches comprises a primary speech path memory, a hold memory, and a time slot counter. In this case, speech signals, each carrying 8 parallel bits, are written into the primary speech path memory upon receipt of addresses read out of the hold memory and are read from the primary speech path memory into the space switch upon receipt of addresses generated by the time slot counter. That is, the primary speech path memory adopts a random write operation and a sequential read operation. Similarly, each of the secondary time switches comprises a secondary speech path memory, a hold memory, and a time slot counter. In this case, the speech signals transmitted from the space switch are written into the secondary speech path memory upon receipt of addresses generated by the time slot counter and are read from the secondary speech path upon receipt of addresses read out of the hold memory. That is, the secondary speech path memory adopts a sequential write operation and a random read operation.
On the other hand, the space switch, which is interposed between the primary time switches and the secondary time switches, comprises gate switches for connecting one of the primary time switches to one of the secondary time switches and further comprises hold memories for controlling the gate switches.
In the above-mentioned prior art, however, although circuits such as the speech memories and the hold memories have a similar configuration, each circuit is constructed by combining general-purpose memory unit elements and general-purpose logic integrated circuits, which complicates the design and manufacture of a digital time-division switching system, thereby increasing the cost thereof.